1. Field of the invention
The present invention relates to a double capacitor and a method of manufacturing the same. The double capacitor has the capability of storing a large amount of electrical charge in a limited area of an ultra-high density semiconductor device. The invention particularly relates to a double capacitor in which two capacitors are connected in parallel to another circuit element and a method of manufacturing the same using lift off and area compensation technologies that are presently used to produce stacking type capacitors and trench type capacitors.
2. Background of the invention
As the density of the semiconductor memory devices increases, manufacturing technologies have been further refined to produce smaller semiconductor chips having an increased number of circuit elements. The size of memory cells is one important factor influencing the size of semiconductor chips.
One important factor in increasing this density and reducing the size of semiconductor chips is the fabrication techniques used to form capacitors capable of storing large amounts of electrical charge in a limited area.
Ordinary plane capacitors having a small size and large capacitance can be formed by reducing the thickness of the insulating layer an amount proportionally greater than the reduced capacitor area. However, in mega-bit scale semiconductor memory devices, reducing the thickness of the dielectric film to a satisfactory degree and using a material having a high dielectric constant is difficult. Therefore, it has been recognized that the need exists for a structurally new capacitor.
One type of structurally different capacitor that has recently been developed is a cell capacitor having a three dimensional structure, which is represented by stacking type capacitors and trench type capacitors.
The stacking type capacitor has a three dimensional structure on the substrate formed in a 3-layer polycrystalline silicon stack structure that can be used for gating transistors in the storage cell and the like. However, step differences between several layers and minimal improvements in dielectric films have made the use of stacking type capacitors in memory devices of over 4 Mb difficult.
The trench type capacitor, which is manufactured using anisotropic silicon etching, also gives an increased effective capacitor area. Further, in the direction of the plane, it provides this increased capacitor area in a narrow space, thereby making it advantageous for semiconductor memory devices having a density over 4Mb. However, a reduced gap between trenches results in leakage currents and processing is difficult and complicated. For instance, the device being manufactured can be damaged or polluted during anisotropic etching using accelerated charged particles. Also, soft errors due to alpha particles are problematic for trench type capacitors.
Related to the use of capacitors in semiconductor memory devices having a high density is the use of transistors with capacitors in a memory cell. Therefore, the connection of the capacitor to the transistor, and the ability to do this using minimum line widths is important. However, if capacitors of the type described above are used, the problems discussed above still exist.